This invention relates to a redundancy circuit for a semiconductor memory device and, more particularly, to a redundancy circuit for saving defective memory cells in a semiconductor memory device of the byte configuration type in which data are read out for each bit.
The integration density as well as the memory capacity of a semiconductor memory device has been increased year by year. Recently, 256 Kilo bits dynamic random access memories (DRAMs) and 64 Kilo bits static random access memories (SRAM) have been put into practice and widely marketed. In manufacturing such memory devices with high integration density and large memory capacity, the problem of the production yield is serious. To cope with this problem, a redundancy technique has been developed. In this approach, an auxiliary memory is formed on the same semiconductor chip with a main memory containing main memory cells in a predetermined memory capacity. If a defective memory cell is contained in the main memory, one of the spare memory cells is used in place of the defective cell. In this way, the production yield in manufacturing the semiconductor memory device is remarkably improved. Actually, however, it is impossible to replace the memory cells one by one. For this reason, in the conventional redundancy circuit, a proper number of row or column spare memory cells are provided. A row or column of the main memory array containing a defective memory cell is replaced by a row or a column in the spare memory arrays. To realize this, a spare row decoder or a spare column decoder associated with the spare memory is programmed so that when a defective cell contained row or column of the main memory is designated, a row or column of the spare memory is correspondingly designated. Fuses are used for program elements, and in programming the decoder, the fuses are selectively burned out by feeding current capable of melting the fuse or by applying a laser beam to the fuse.
FIG. 1 shows a conventional redundancy circuit with a program circuit in which fuses are selectively burned out in an electrical manner for the progamming. FIG. 2 shows the program circuit of the above redundancy circuit in which N channel MOS transistors are used for the programming elements. In FIG. 1, address signals Ao, Ao to An, An are applied to a main decoder 1 and program circuits 2.sub.1 to 2.sub.n. The output signals from the program elements 2.sub.1 to 2.sub.n, together with a spare row enable signal, are input to a spare row decoder 3. The output signal from the spare row decoder 3 is applied to a spare row 5 in a memory cell array 4. The output signal of the spare row decoder 3 is connected to a NOR gate 6. The output signal of the NOR gate 6 is inverted in level by an inverter 7 and is applied as a disable signal for the main decoder to the main decoder 1. The output signal of the main decoder 1 is input to a main row 8.
In FIG. 2, Ai and Ai designate address signals, respectively. MOS transistors 21-25 are of the enhancement type. MOS transistors 26 and 27 are of the depletion type. Reference numerals 28 and 29 stand for an inverter and a fuse, respectively. Address signals Ai and Ai are respectively connected to first ends of the current paths of the transistors 21 and 22. The second ends of these current paths are interconnected with each other to provide an output terminal of the redundancy circuit. The transistor 26 is connected at the drain to a programming power source Vp. The source of the transistor 26 is connected to the drains of the transistors 23 and 24 and the gate of the transistor 25. The gate of the transistor 26 is connected to the source thereof. A programming signal is applied to the gate of the transistor 23 of which the source is grounded. The address signal Ai is connected to the gate of the transistor 24 of which the source is grounded. The transistor 25 is grounded at the source and connected at the drain to one end of a fuse 29, the drain of the transistor 27, and the gate of the transistor 22. The drain of the transistor 25 is further connected through an inverter 28 to the gate of the transistor 21. The source of the transistor 27 is interconnected with the gate thereof, and further is grounded. The other end of the fuse 29 is connected to a power supply Vcc. The same thing is correspondingly applied to the other program circuits. In the example of FIG. 2, the fuse 29 is burned out by the program signal. With burning out the fuse 29, the address signal Ai or Ai is selected. When the fuse 29 is not melted, a Vcc potential (high level) is connected to the gate of the transistor 22 and the inverter 28 through the fuse 29. Then, the transistor 22 is turned on, while the transistor 21 is turned off by a low level output from the inverter 28. Accordingly, the address signal Ai is output to the output terminal 12 of the program circuit. On the other hand, when the fuse 29 is burned out, a low level potential is applied to the gate of the transistor 22 and the inverter 28. Then, the transistor 22 is turned off, and the transistor 21 is turned on since it receives a high level signal from the inverter 28. Accordingly, the address signal Ai is output.
For burning out the fuse 29, the programming signal is set at a low level, and the address signal Ai is also set at a low level. Then, the transistors 23 and 24 are both turned off. Accordingly, a high level potential is applied through the transistor 26 to the gate of the transistor 25. And the transistor 25 is turned on. As a result, a large current flows through the fuse 29, and then it is burned out.
In the redundancy circuit of FIG. 1, if the main memory has no defective memory cell, the spare row enable signal is kept at high level. Therefore, the output of the NOR gate 6 is high in level, and the output of the inverter 7 is low. Only the main decoder 1 operates to select a main row. When the main memory contains a defective memory cell, an address of the row containing the defective memory cell is selected and the fuse 29 is melted for programming. Further, the spare row enable signal is programmed to be in low level and to cause the spare row decoder 3 to operate. When the defective memory cell is designated through such programming, the output of the spare row decoder designated corresponding to the main row containing the defective memory cell is high in level. Then, the spare row 5 applied with the high level output is selected. The output of the NOR gate 6 is low and the output of the inverter 7 is high. As a result, the main decoder 1 is in the non-select state.
The circuit arrangement of the redundancy circuit as shown in FIG. 1 is easily assembled into a bit configuration type memory device in which data is read out bit by bit. For assembling the redundancy circuit into a byte configuration type memory device in which data is read out byte by byte, the circuit must be designed so that a single or a plurality of the spare rows or columns is switched among a plurality of inputs and outputs. Such a configuration makes the circuit construction complicated, and further deteriorates the write and read out speed performance of the memory device. The byte-configuration-memory device may be modified so as to have a redundancy function, if the spare row or column is provided for each bit of one byte. Such an approach, however, requires a number of spare rows or columns which is equal to that of bits of one byte. For example, four spare rows or columns are required for four bits; eight spare rows or columns for eight bits. Such a circuit configuration requires a large chip area of the semiconductor memory device. The result is a reduction of the production yield in manufacturing the semiconductor memory devices.